1. Field of the Invention
The present invention generally relates to a circuit for driving a VCO (voltage controlled oscillator) of a frequency synthesizer. More particularly, the present invention relates to a VCO driving circuit and a frequency synthesizer using the same, in which the impedance as viewed from a VCO control terminal is reduced to prevent degradation of the VCO phase noise characteristics.
2. Description of the Related Art
A frequency synthesizer using a PLL (phase locked loop) is known as one of the standard signal generators.
[Conventional Frequency Synthesizer: FIG. 26]
A conventional frequency synthesizer will be described with reference to FIG. 26. FIG. 26 shows a schematic configuration diagram of the conventional frequency synthesizer.
As shown in FIG. 26, the conventional frequency synthesizer basically includes an oscillator 21 that oscillates at a reference frequency signal fref, a frequency divider 22 that divides the frequency signal to 1/M, a phase comparator (PLL IC) 23 that compares a phase of a reference signal from the frequency divider 22 with a phase of an output signal from a frequency divider 27 to thereby output a phase difference signal, a charge pump 24 that outputs the phase difference as a pulse width voltage, an LPF (low pass filter) 25 that smoothes out the output voltage from the charge pump 24, a VCO 26 that changes a frequency based on a control voltage from the LPF 25 to thereby oscillate a desired frequency, and the frequency divider 27 that branches out and receives the output frequency from the VCO 26 to thereby divide the output frequency to 1/N and outputs the divided frequency to the phase comparator 23.
The phase comparator 23 is implemented in the form of a PLL IC. Moreover, the frequency dividers 22 and 27 are usually in the form of a counter.
Moreover, the LPF 25 is generally in the form of a lag filter shown in FIG. 27 or a lead-lag filter shown in FIG. 28. FIG. 27 shows a configuration diagram of a lag filter, and FIG. 28 shows a configuration diagram of a lead-lag filter.
As shown in FIG. 27, the lag filter is a filter composed of a resistor R and a capacitor C.
As shown in FIG. 28, the lead-lag filter is a filter composed of two resistors R1 and R2 and one capacitor C.
The frequency synthesizer of FIG. 26 is a PLL oscillator that performs a feedback control by the phase comparator 23 detecting a phase difference so that the phase of the VCO 26 is maintained at a constant value relative to the phase of a reference signal.
Usually, a plurality of such configurations is arranged in an apparatus.
An example of the prior art of such a frequency synthesizer is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2004-274673 (Patent Document 1).
[Another Frequency Synthesizer: FIG. 29]
Another conventional frequency synthesizer will be described with reference to FIG. 29. FIG. 29 shows a schematic configuration diagram of another conventional frequency synthesizer.
The frequency synthesizer shown in FIG. 29 basically includes an oscillator 21 that oscillates at a reference frequency signal fref, a frequency divider 22 that divides the frequency signal to 1/M, a phase comparator (PLL IC) 23 that compares a phase of a reference signal from the frequency divider 22 with a phase of an output signal from a frequency divider 27 to thereby output a phase difference signal, a charge pump 24 that outputs the phase difference as a pulse width voltage, an LPF (low pass filter) 25 that smoothes out the output voltage from the charge pump 24, a VCO 26 that changes a frequency based on a control voltage from the LPF 25 to thereby oscillate a desired frequency, the frequency divider 27 that receives and branches off the output frequency from the VCO 26 to thereby divide the output frequency to 1/N and outputs the divided frequency to the phase comparator 23, a CPU (central processing unit) 28 that gives data setting timings to the frequency divider 27 and outputs a data value of a preset voltage corresponding to a setting frequency, a D/A converter (DAC) 29 that A/D converts the data value of the preset voltage from the CPU 28, and an adder 30 that adds the preset voltage from the DAC 29 to the output from the LPF 25.
The preset voltage corresponding to the setting frequency is added by the adder 30 at the rear stage of the LPF 25. Therefore, the output voltage of the LPF 25 is locked by the PLL circuit with small voltage fluctuation required for error correction, and thus the lock time can be shortened.
According to another example of the prior art, Japanese Unexamined Patent Publication (Kokai) No. 05-090993 (Patent Document 2) discloses a PLL frequency synthesizer having two loop filters which are alternately switched upon high speed switching of an output high-frequency signal.
According to another example of the prior art, Japanese Unexamined Patent Publication (Kokai) No. 10-173521 (Patent Document 3) discloses a PLL circuit that uses a normal VCO to reduce externally attached components and to allow performing a pull-in operation even when an oscillation frequency of the VCO is deviated due to fluctuation in manufacturing. The PLL circuit includes a multiplexer that is inserted between a phase comparator and a loop filter, a PWM signal generator that generates a PWM-L signal having a low duty factor and a PWM-H signal having a high duty factor based on a reference clock, and a frequency determining circuit that determines as to whether or not the frequency of a dividing signal is within a predetermined frequency range based on the reference clock and that transmits a switching signal according to the result of the determination to the multiplexer. When the frequency of the dividing signal is within the predetermined range, the output of the phase comparator is supplied to the loop filter, while when it is higher than the predetermined range, the PWM-L signal is supplied to the loop filter, and when it is lower than the predetermined range, the PWM-H signal is supplied to the loop filter.
According to another example of the prior art, Japanese Unexamined Patent Publication (Kokai) No. 11-185395 (Patent Document 4) discloses a clock reproduction PLL unit that prevents PLL unlock due to temperature variation and generates a reference voltage with high accuracy with a resolution finer than a phase difference signal. In the PLL unit, an 8-bit phase difference signal is input from a phase comparator to one input of a differential amplifier, while reference data having a resolution of 12 bits having been modulated in a time base direction in a data modulation circuit are input to the other input of the phase comparator, whereby a control voltage is generated based on a reference voltage substantially having a resolution of 12 bits.
Patent Document 1: Japanese Unexamined Patent Publication (Kokai) No. 2004-274673
Patent Document 1: Japanese Unexamined Patent Publication (Kokai) No. 05-090993
Patent Document 1: Japanese Unexamined Patent Publication (Kokai) No. 10-173521
Patent Document 1: Japanese Unexamined Patent Publication (Kokai) No. 11-185395
However, in the conventional frequency synthesizers described above, when driving circuits such as the charge pump 24, the LPF 25, and the like, connected to the control terminal of the VCO 26 has a high impedance, the phase noise characteristics of the VCO 26 is degraded at an offset frequency of several kHz or less. Therefore, there is a problem that the VCO 26 driven with high impedance may be unable to suppress the noise even when the PLL is successfully locked.
In such a case, since the high impedance is in the order of several hundreds of ohms [Ω], a normal lag-lead filter cannot cope with such a problem.